SZ2N-48MT-4HS

CPU	ARM 32-bit Cortex-M3 CPU
Digital Input	24, NPN transistor input x 24, supporting source/ drain type
Digital Output	24, NPN transistor output x 24
High-Speed Input	2-way AB input/4-way separate high-speed Counting
High-Speed Output	4-way high speed surge immunity output (100kHz x 2, 50kHz x 2)
User Program Memory	200K Bytes (>10K Bytes)
Involatile Data Memory	2K Bytes
Timer	256, 100ms timer x 206 (0.1~3276.7 seconds), 10ms timer x 46 (0.01~327.67 seconds), 1ms timer x 4 (0.001~32.767 seconds)
Counter	235
High-speed Interrupt	X0-X5 rising and falling edge interruption, 3-way timing interruption
Program Execution Model	Cycling scanning
Execution Speed	0.1us/1000AWL (ON : 5us/OFF : 5us)
Programming Language	Ladder diagram/standard C program (both can be used)
Comunication Protocol	Rs232 x 1, RS485 x 1, Supporting Mitshubish FX2N and Modbus RTU communication
Programming Port	Programming Port USB connection
Power Consumptiont	4W
Input Power	DC 24V, Input Range: DC 18V~28V
Power Protection	Isolated Power, protect from surging and thunder strike
Power Down Allowed	<5ms
CE & ROHS	Complied with EN61000-6-2:2005, EN61000-6-4:2007 standard, ROHS Surge Immunity: ±1KV, EFT:±2KV, ESD:4KV, Air: 8KV
Operating Temperature	-20°C to 70°C
Storage Temperature	-30°C to 80°C
Operation Humidity	10 to 90% RH (No condensation)